# Makefile Script

VIVADO := /home/airxs/software/xilinx/Vivado/2022.2/bin/vivado
ifeq (, $(shell which $(VIVADO)))
 VIVADO := vivado 
endif

VIVADO += -mode batch -nojournal

WORKS := impl/work-xlnx
XILINX_IPS_DIR := ip

# project name 
PROJECT = labcore
PROJECT_HOME = $(shell pwd)
SYNTH_TOP_MODULE = Soc_xlnx

BOARD := vcu118
# BOARD := vcu129
XILINX_BOARD := 
XILINX_PART := 

# Here export this parameter, after we use then in vivado project 
export PROJECT
export PROJECT_HOME
export BOARD

ifeq ($(BOARD), vcu129)
	XILINX_BOARD := xilinx.com:vcu129:part0:1.0
	XILINX_PART := xcvu29p-fsga2577-2L-e
else ifeq ($(BOARD), vcu118)
	XILINX_BOARD := xilinx.com:vcu118:part0:2.4
	XILINX_PART := xcvu9p-flga2104-2l-e
else ifeq ($(BOARD), v709)
	XILINX_BOARD := xilinx.com:vc709:part0:1.8
	XILINX_PART := xc7vx690tffg1761-2
else 
	$(error ERROR: NOT MATCH BOARD Configuration)
endif

export XILINX_PART
export XILINX_BOARD

$(info project_home: $(PROJECT_HOME))

XILINX_IPS := 	axi_clock_converter.xci  \
				sram.xci


ifeq ($(BOARD), vcu129)
	XILINX_IPS := xlnx_dwidth_converter.xci \
				  xlnx_clock_converter.xci \
	              xlnx_ddr4.xci  \
	              xlnx_clk_wiz.xci

else ifeq ($(BOARD), vcu118)
	XILINX_IPS := xlnx_dwidth_converter.xci \
	              xlnx_clock_converter.xci \
	              xlnx_ddr4.xci \
	              xlnx_clk_wiz.xci \
	              xlnx_reset.xci

	XILINX_IPS := xlnx_clock_converter.xci \
				  xlnx_vio.xci 
endif

IPS := $(addprefix $(WORKS)/, $(XILINX_IPS))


all: compile gen_mcs

# Generate seperate project and get xci 
$(IPS): %.xci :	
	mkdir -p $(WORKS)
	@echo Generating $(@F)
	@cd $(XILINX_IPS_DIR)/$(basename $(@F)) && make compile_ip
	cp $(XILINX_IPS_DIR)/$(basename $(@F))/$(basename $(@F)).srcs/sources_1/ip/$(basename $(@F))/$(@F) $@


VIVADO_RUN_TCL := ../../scripts/run.tcl


BIOS_NAME := bios
BIOS:
	make -C ext/bios all
	./scripts/gen_axi_rom.py ./ext/bios/$(BIOS_NAME).hex

compile: BIOS $(IPS)
	mkdir -p $(WORKS)
	rm -rf ext/rtl/board.h
	./scripts/gen_board_config.py -board-name $(BOARD)
	./scripts/gen_vivado_labcore.py
	cp ext/bios/inst_ram.coe ext/bios/data_ram.coe $(WORKS)
	cd $(WORKS) && $(VIVADO) -source $(VIVADO_RUN_TCL)
	cd $(WORKS) && cp $(PROJECT).runs/impl_1/$(SYNTH_TOP_MODULE).* .

run_impl:
	cd $(WORKS) && $(VIVADO) -source ../../scripts/open_run_impl.tcl
	cd $(WORKS) && cp $(PROJECT).runs/impl_1/$(SYNTH_TOP_MODULE).* .


LOADER_DIR     := ext/loader

BIOS_ELE       := ext/loader/loader.bin
BIOS_FILE      := bios.bin
BIOS_OFFSET    := 0x1c000000

KERNEL_ELF     := ext/loader/vmlinux.bin
KERNEL_FILE    := vmlinux.ddr
KERNEL_OFFSET  := 0x200000

UP_BIT_FILE := vmlinux.ddr.upload

LINUX_DIR := /home/airxs/user/cpu/dev/system/linux/linux-4.19-labcore

vmlinux:
	make -C $(LINUX_DIR) -j10
	make -C $(LOADER_DIR) clean
	make -C $(LOADER_DIR)
	cd $(WORKS) && rm -rf $(UP_BIT_FILE) $(BIOS_FILE) $(KERNEL_FILE)
	cd $(WORKS) && cp ../../$(BIOS_ELE) $(BIOS_FILE)
	cd $(WORKS) && cp ../../$(KERNEL_ELF) $(KERNEL_FILE)
	cd $(WORKS) && ../../scripts/gen_upload_data.py \
					$(BIOS_FILE)   $(BIOS_OFFSET) \
					$(KERNEL_FILE) $(KERNEL_OFFSET) \
					$(UP_BIT_FILE)

upload: vmlinux
	$(VIVADO) -source scripts/download_bit_ddr_and_run.tcl -tclargs $(WORKS) $(WORKS)/$(UP_BIT_FILE)


MCS := $(SYNTH_TOP_MODULE).mcs
BIT := $(SYNTH_TOP_MODULE).bit

gen_mcs: compile
	cd $(WORKS) && $(VIVADO) -source ../../scripts/gen_mcs.tcl -tclargs $(MCS) $(BIT)

clean:
	rm -rf $(WORKS)/* $(WORKS)/.Xil .Xil
	make -C verif/vcs/hello clean
	make -C verif/vcs/coremark clean
	make -C verif/vcs/kernel clean
	make -C verif/verilator/MiniSim clean
	make -C verif/verilator/VerSim clean
	make -C ext/bios clean
	make -C ip/xlnx_clk_wiz clean
	make -C ip/xlnx_dwidth_converter clean
	make -C ip/xlnx_clock_converter clean
	make -C ip/xlnx_ddr4 clean
	make -C ip/xlnx_reset clean
	make -C ip/xlnx_vio clean


.PHONY: compile clean
